The present invention relates to a semiconductor memory device, and more particularly relates to an improved dynamic random access memory (DRAM).
In recent years, DRAMs have been drastically downsized to further increase the number of semiconductor devices, including memories like DRAMs, integrated on a single chip. In order to ensure the selection of a desired word line from an array of such miniaturized memories, a so-called "hierarchical word line implementation" has been adopted these days with the pitch of metal interconnects somewhat increased. This technique is disclosed in "A 29-ns 64-Mb DRAM with Hierarchical Array Architecture", IEEE J. Solid State Circuits, Vol. 31 (1996), pp. 1302-1307, for example.
FIG. 7 illustrates this exemplary prior art DRAM disclosed in this document. In the DRAM shown in FIG. 7, an array a of memory cells (hereinafter, simply referred to as an "array a") is divided into a plurality of sub-arrays b. A set of sub-arrays b, which are arranged on the same row, collectively forms a single block 0, 1, 2, 3 and so on. A plurality of main word lines GWL are also provided for this array a. Several ones of the main word lines GWL, associated with a single block, extend over all of the sub-arrays b included in the block. It should be noted that only a single main word line GWL is illustrated in FIG. 7 for the sake of simplicity. And each of these word lines GWL is driven by an associated row decoder (not shown) to be selected responsive to a predetermined address signal. A plurality of (e.g., four in FIG. 7 as indicated by the bold lines) sub-word select lines Dxi are further arranged to cross the main word lines GWL at right angles in this array a. Each of these sub-word select lines Dxi is shared in common by an associated set of sub-arrays b arranged on the same column. In response to a common address signal composed of several (e.g., two) bits, one of the sub-word select lines Dxi is selected. Once one of the main word lines GWL and one of the sub-word select lines Dxi have been selected, one of a plurality of sub-word drivers (not shown) is automatically selected. The selected sub-word driver drives one of a plurality of sub-word lines (not shown) that are connected to respective memory cells.
Next, the operation of this prior art DRAM will be described. Responsive to a row address supplied, one of the row decoders is selected and a single main word line GWL, which is connected to the selected row decoder, is selected and enabled. At the same time, in response to another row address, which is different from the former row address for selecting the single main word line, one of the sub-word select lines Dxi is selected and enabled. Once the particular main word line GWL and the particular sub-word select line Dxi have been enabled at a desired sub-array b, associated one of the sub-word drivers (not shown) is selected. And a single sub-word line that is connected to the selected sub-word driver is selected and enabled. As a result, information is read out from a memory cell connected to the sub-word line.
In this conventional DRAM with the hierarchical word line implementation, a predetermined time margin is required between the enablement or disablement of a main word line and the enablement or disablement of a sub-word select line. This point will be detailed below. A sub-word driver, including only n-channel MOS transistors, is implemented as a self-booster to increase a voltage level on the associated sub-word line to a boosted level. In accordance with this self-boosting technique, if a main word line is selected, the gate voltage at a sub-word driver increases. At a point in time when the gate voltage reaches a level sufficiently higher than the boosted level, the associated sub-word select line should be enabled. Accordingly, a timing margin should be secured for self-boosting between the enablement of the main word line and that of the sub-word select line. No matter whether a sub-word driver includes only n-channel MOS transistors or is a CMOS including both n- and p-channel MOS transistors, the sub-word driver can disable the associated sub-word line faster if the driver turns OFF the MOS transistors between the associated sub-word select line and the sub-word line by disabling the sub-word select line, not just by turning ON the n-channel MOS transistors between the sub-word line and the ground. In this case, in order to disable the sub-word line effectively by disabling the sub-word select line, the main word line should not be disabled until the sub-word select line has been disabled. That is to say, a timing margin should be provided between the disablement of the sub-word select line and that of the main word line.
In the conventional DRAM with the hierarchical word line implementation, however, the main word lines and the sub-word select lines are arranged to cross each other at right angles over a plurality of sub-arrays. Thus, in enabling a sub-array located far away from the start end of a main word line (i.e., an end of the line closer to a decoder as a signal source), the enablement of a sub-word select line, associated with the sub-array, should be much delayed even if the sub-array is located near the start end of the sub-word select line. This is because the sub-word select line should not be enabled until the main word line has been enabled in this sub-array. That is to say, a large timing margin should be secured between the enablement of the main word line and that of the sub-word select line, thus increasing the time required to access such a DRAM and interfering with the high-speed operation of the DRAM. The same statement applies to a timing margin to be secured between the enablement of a main word line and the disablement of a sub-word select line.